ABCDE: Why should we invest in Cysic?
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ABCDE: Why should we invest in Cysic?
Cysic is an industry-leading ZK hardware acceleration project dedicated to designing advanced ASIC chips to help reduce ZK proof generation time.
Navigating Web3 tides with focused insightsAuthor: Siyuan Han
Cysic is a leading ZK hardware acceleration project in the industry, dedicated to designing advanced ASIC chips to reduce the time required for ZK proof generation. Cysic has assembled a world-class hardware design and R&D team and has already completed its FPGA-based POC design. The POC results demonstrate that Cysic's ZK hardware acceleration capabilities are already at the forefront of the industry.
ABCDE invested in Cysic during its Seed round, alongside other participating investors including Polychain, A&T Capital, Hashkey, and Web3.com Venture.
1. Why We Need ZK Hardware Acceleration
ZK proof generation is one of the most critical steps in any ZK project. Unfortunately, under existing ZK proof systems, generating ZK proofs typically requires massive computational power. As project complexity increases and ZK circuit sizes grow, the computational demands of ZK proof generation rise exponentially. For large-scale zkEVM/zkVM projects such as Scroll and zkSync, relying solely on CPUs for ZK proof generation could take hours or even days. In real-world applications, most projects need to limit ZK proof generation to just seconds or minutes. Computation times lasting hours—or longer—are completely unacceptable for most ZK projects, especially scalability-focused projects like zkEVM/zkVM.
Moreover, in the two-year window before most ZK projects go live, there is little possibility of reducing the computational complexity of ZK proof generation from a theoretical standpoint. Therefore, to ensure practical usability, ZK projects must adopt "accelerated ZK proof generation" technologies to bring proof generation down to seconds or minutes. Currently, the preferred approach is to use high-performance hardware acceleration.
What Does Hardware Accelerate?
During ZK proof generation, the most time-consuming computations fall into two main categories: 1) NTT (Number Theoretic Transform) based on polynomials, and 2) MSM (Multi-Scalar Multiplication) performed on elliptic curves, as shown in the figure below [1]. Typically, NTT operations account for about 25% of total computation in a single ZK proof generation, while MSM operations make up approximately 60–70% [2].
Fortunately, these two types of computations share the following characteristics:
1. Relatively simple logic,
2. Large amounts of repetitive computational logic,
3. High parallelizability—similar to Bitcoin mining computations. Thus, accelerating these two types of computations using high-performance hardware is theoretically feasible.
As illustrated below, we can see that NTT (top-left) and MSM (right) computations are loosely coupled within the ZK proof generation workflow. Therefore, ZK projects can choose from three options depending on their specific needs:
1. Accelerate only NTT, or
2. Accelerate only MSM, or
3. Accelerate both NTT and MSM together.
General Workflow of ZK Proof Generation [1]
Note 1: The above image comes from a paper by Scroll co-founder Zhang Ye titled "PipeZK: Accelerating Zero-Knowledge Proof with a Pipelined Architecture." This is one of the earliest academic works exploring ZK hardware acceleration.
Note 2: Some literature/articles claim that FFT (Fast Fourier Transform) and MSM are the most time-consuming parts of ZK proof generation. Although FFT and NTT are conceptually similar, cryptographic computations in ZK occur over finite fields, making NTT the correct term used in practice. We follow the majority of academic papers that use NTT [1][2][3].
What Hardware Is Used for Acceleration?
Similar to cryptocurrency mining, current ZK hardware acceleration solutions primarily rely on three types of hardware:
- GPU
- FPGA
- ASIC
Currently, GPU and FPGA are the main hardware acceleration options available on the market. GPU/FPGA-based acceleration is relatively easier to implement, so most vendors opt for these first to capture market share quickly. However, due to higher hardware costs, greater power consumption, and limited peak performance, ASIC remains an indispensable part of the ZK hardware acceleration ecosystem.
How Do Hardware Acceleration Providers Serve ZK Projects?
ZK hardware acceleration providers can offer proof generation acceleration services in two ways:
1. Via SaaS APIs.
2. By selling hardware (full machines/chips), similar to selling mining rigs.
As mentioned earlier, NTT and MSM computations are loosely coupled during ZK proof generation. Therefore, depending on service granularity, hardware acceleration providers can offer three levels of service:
1. Dedicated NTT acceleration (via specialized NTT acceleration API/hardware device)
2. Dedicated MSM acceleration (via specialized MSM acceleration API/hardware device)
3. Integrated solution accelerating both NTT and MSM simultaneously
Differences Among Hardware Acceleration Providers
The computational problems behind NTT and MSM have been widely studied for years. It is difficult for vendors to achieve breakthroughs at the theoretical level in the short term. As a result, technical differentiation among vendors lies more in engineering implementation capability, fine-grained algorithm optimization, choice of technology stack (hardware), cost control in hardware production, and product design. When selecting a hardware acceleration provider, customers typically prioritize three key factors:
1. Performance of hardware/service—the time required by the vendor to complete the same computational task.
2. Cost of hardware acceleration—the cost incurred by the vendor for the same computational task.
3. Ease of use of the API/device.
2. Why We Invested in Cysic
Cysic was founded in late August 2022 by Leo Fan and Bowen Huang, with the primary goal of providing hardware acceleration services for the ZK proof generation process in ZK projects. The founding team members come from top-tier institutions, including PhDs from top 20 U.S. universities and chip design teams from the Institute of Computing Technology, Chinese Academy of Sciences. Currently, the project has achieved POC validation for FPGA-based MSM computation, codenamed SolarMSM. At this stage, SolarMSM will be offered as a SaaS service. Cysic has already reached cooperation intentions with several leading ZK projects and will soon provide them with testing services. According to multiple industry experts, SolarMSM ranks among the top-tier in terms of MSM computation acceleration performance.
Founding Team Overview
The two founders possess exceptional technical backgrounds, specializing respectively in cryptography and hardware design. Leo holds a PhD from Cornell University, where he studied under renowned cryptographer Elaine Shi. Prior to joining Rutgers University as an assistant professor, Leo worked as a cryptography researcher at Algorand.
The other founder, Bowen Huang, spent six years working at the Institute of Computing Technology, Chinese Academy of Sciences, and later pursued his PhD at Yale University. He has previously participated in chip development at several well-known tech companies and holds multiple patents and successful designs.
POC Results
Cysic has successfully completed the POC design of an MSM acceleration solution based on Xilinx’s off-the-shelf FPGAs, codenamed SolarMSM. During POC validation, SolarMSM completed an MSM computation with input size 2³⁰ in **under one second** [2]—the best publicly reported performance to date, outperforming the winning entry of the ZPrize competition by 1–2 orders of magnitude.
SolarMSM’s rapid realization demonstrates:
1. Cysic’s highly efficient R&D strength and technical capabilities. Achieving performance 1–2 orders of magnitude faster than the ZPrize winner showcases overwhelming speed advantages.
2. Cysic’s robust supply chain integration and management capability. Despite parallel custom designs across PCB, cooling, power delivery, PCIe connectors, and chassis structure, Cysic delivered within 2–3 months—approximately 2–3 times faster than industry standards.
Additionally, this POC serves as internal validation for Cysic’s hardware design/R&D efforts. Since ASIC chip error correction is far more costly than FPGA-based solutions, thorough real-world testing under high bandwidth, high power, and high interconnectivity conditions significantly reduces the risk of future ASIC failures.
Technology Roadmap
Cysic plans to deliver a full ASIC-based hardware acceleration solution covering both NTT and MSM computations. The project follows a two-phase development strategy.
Phase One: FPGA-Based POC
In the first phase, Cysic implements POC versions of MSM and NTT acceleration using Xilinx’s standard FPGAs: SolarMSM. The MSM acceleration module is now complete, capable of finishing a 2³⁰-scale MSM computation in less than **one second**, achieving the highest performance among all publicly disclosed FPGA-MSM hardware acceleration results, outperforming competitors by 1–2 orders of magnitude. Unless unexpected delays occur, SolarMSM will maintain the performance lead until ASICs become available. Cysic has reached cooperation agreements with several leading ZK projects and will initially offer them MSM acceleration services.
Over the next few months, Cysic plans to complete the NTT acceleration module, SolarNTT, building upon SolarMSM. SolarNTT will be deployed on the same server as SolarMSM, leveraging the same large-scale FPGA interconnection system for accelerated computing. These two modules will be integrated via Cysic’s high-speed interconnect architecture into a unified acceleration solution called SolarZKP, which will be offered externally via SaaS APIs.
Phase Two: 12nm ASIC
After the POC phase, Cysic will begin developing a 12nm ASIC. The goal is to match the performance of the entire SolarZKP system on a single ASIC chip (supporting both MSM and NTT computations, plus other core functions specified by clients), while reducing power consumption by two orders of magnitude.
3. Market Analysis
How Customers Choose Hardware Acceleration Solutions
In practice, different ZK customers have varying needs for hardware acceleration, depending on their sensitivity to proof generation time. For example:
• For zkEVM/zkVM-based Layer-2 projects, the core requirement is fast and stable ZK proof generation. They tend to prefer faster, more reliable integrated acceleration solutions.
• For ZK projects less sensitive to proof generation time—such as exchange proof-of-reserves—speed is not critical. In such cases, customers may flexibly choose options like dedicated MSM acceleration, or combine MSM and NTT services from different providers to achieve optimal pricing within acceptable timeframes.
We believe tools will emerge in the future to help customers optimize combinations of hardware acceleration solutions from different vendors.
4. Project Risks
Currently, multiple companies are competing in the ZK hardware acceleration space. ASIC-based ZK hardware acceleration projects face risks related to development delays and market adoption.
Development Delay Risk
There is a mutually reinforcing relationship between ZK projects and ZK hardware acceleration providers. ZK projects typically adopt the first viable hardware acceleration solution to gain market share early. For zkEVM/zkVM projects, reliably producing L2 block proofs is a top priority. As a result, some ZK projects enter long-term partnerships with hardware acceleration providers early on. If development lags, they risk losing early market share. Additionally, ASIC tape-out carries inherent failure risks. Due to foundry capacity constraints, a failed tape-out forces the project to reschedule, causing significant delays.
Market Risk
ZK projects can be broadly categorized into privacy-focused and scaling-focused types. Privacy-oriented projects may cautiously adopt hardware acceleration—even if it reduces side-channel attack risks—due to data confidentiality concerns. They may prefer purchasing hardware directly rather than using SaaS-based services.
5. Competitor Landscape
Top Competitors
Currently, there are three major competitors in the space: Supranational, Ulvantanna, and Auradine.
Supranational
Supranational entered the GPU-accelerated ZK space in 2019 and has recently expanded into FPGA/ASIC domains. It already offers mature open-source GPU acceleration solutions with industry-leading performance. Additionally, Supranational likely has a superior closed-source commercial version. With an early market entry, strong industry connections, and solid cash flow, it remains a formidable player.
Ulvantanna
Founded by talent from Jump Crypto and backed by Paradigm and Bain Crypto, Ulvantanna possesses considerable strength.
Auradine
The founding team is experienced, with extensive entrepreneurial background and support from top-tier firms and investors.
Other Hardware Acceleration Teams
Other teams such as Ingonyama and Jump Crypto entered the space earlier but currently lag behind Cysic’s SolarMSM in publicly disclosed performance metrics.
In-House Hardware Acceleration Teams at ZK Projects
Besides dedicated acceleration teams, many ZK projects are also developing internal hardware acceleration solutions, such as zkSync and Scroll.
zkSync
zkSync adopted a GPU/FPGA acceleration approach. According to public results from ZPrize, zkSync’s GPU solution takes 2.528 seconds to compute a 2²⁶-scale MSM—less than one-tenth the performance of Cysic’s SolarMSM (which completes a larger 2³⁰ MSM in under one second).
Scroll
Scroll has conducted internal research on GPU-based acceleration and is collaborating with academic institutions to explore better solutions. Their latest academic work was presented at ASPLOS 2023, a top conference in computer architecture. As a leading zkEVM project, Scroll’s future progress warrants close attention.
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