Understanding the Profit Pools and Industry Landscape of AI Storage Tiers
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Understanding the Profit Pools and Industry Landscape of AI Storage Tiers
These three directions will determine the shape of the profit pool at each level over the next five years.
Navigating Web3 tides with focused insightsAuthor: Godot
AI storage can be divided into six layers:
1) On-chip SRAM
2) HBM
3) Motherboard DRAM
4) CXL pooling layer
5) Enterprise-grade SSDs
6) NAS and cloud object storage
This hierarchy is defined by physical location relative to the compute unit—the farther down the stack, the greater the storage capacity but the greater the distance from the compute unit.
In 2025, the total addressable market (TAM) across these six layers—excluding embedded SRAM value (since SRAM is integrated onto compute chips)—is approximately $22.9 billion. DRAM accounts for half of this, HBM 15%, and SSDs 11%.
Profitability across each layer is characterized by extreme oligopolistic concentration, with the top three players holding over 90% market share in the first three layers.
These profit pools can be categorized into three types:
1) High-margin, silicon-layer oligopoly pools (HBM, embedded SRAM, QLC SSD)
2) High-margin, emerging interconnect-layer pools (CXL)
3) Scale-driven, compounding service-layer pools (NAS, cloud object storage)
Each pool differs in nature, growth rate, and moat strength.
Why does storage need to be layered?
Because CPUs (which handle control logic) and GPUs (which handle computation) contain only small, temporary caches—on-chip SRAM. This cache is too small to store large language models (LLMs) or even full inference contexts.
Thus, external, larger memory is required outside these chips to store LLMs and inference context.
Data movement between layers introduces latency and energy overhead—and that is the core challenge.
Three main technical directions are currently being pursued:
1) Stacking more HBM adjacent to GPUs to minimize data movement distance
2) Using CXL to pool memory at the rack level for shared capacity
3) Integrating compute and storage on the same die—“in-memory computing” or “compute-in-memory”
These three directions will define the shape of each layer’s profit pool over the next five years.
Below is a detailed breakdown by layer:
L0 On-chip SRAM: TSMC’s exclusive profit pool
SRAM (Static Random-access Memory) serves as the on-die cache inside CPUs and GPUs—it is embedded directly into each chip and is not sold separately.
The standalone SRAM die market is tiny—only $1–1.7 billion—with leaders including Infineon (~15%), Renesas (~13%), and ISSI (~10%).
The real profit pool lies with TSMC: every generation of AI chips requires more SRAM area, which translates into higher wafer demand. Over 70% of advanced-node wafers globally are manufactured by TSMC. Every square millimeter of SRAM area in chips like the H100, B200, or TPU v5 ultimately becomes TSMC revenue.
L1 HBM: The largest profit pool in the AI era
HBM (High Bandwidth Memory) stacks DRAM (Dynamic Random-access Memory) vertically using Through-Silicon Via (TSV) technology and integrates it next to GPUs via CoWoS packaging—delivering ultra-high bandwidth.
HBM is practically the sole determinant of how large an AI accelerator can run. SK Hynix, Micron, and Samsung collectively hold ~100% market share.
As of Q1 2026, the latest market share breakdown is: SK Hynix 57–62%, Samsung 22%, Micron 21%. SK Hynix has secured large procurement contracts from NVIDIA and others, making it the dominant supplier today.
Micron stated in its Q1 FY2026 earnings call that the HBM TAM is projected to grow at a ~40% compound annual growth rate (CAGR), rising from ~$3.5 billion in 2025 to $10 billion by 2028—a timeline accelerated by two years versus prior forecasts.
HBM’s key advantage lies in its exceptionally high profitability. In Q1 2026, SK Hynix achieved a record-breaking operating margin of 72%.
Key drivers of this high margin include:
1) TSV manufacturing consumes part of traditional DRAM capacity, keeping HBM supply tight;
2) Advanced packaging yield improvement remains difficult—Samsung’s share dropped from ~40% to 22% partly due to this;
3) Major suppliers have expanded capacity cautiously and achieved >60% sequential increases in DRAM average selling price (ASP) in Q1 2026—clear evidence of seller-market dominance.
Among the “Big Three,” SK Hynix’s strong HBM performance propelled its full-year 2025 operating profit to ₩47.21 trillion—surpassing Samsung Electronics for the first time in history. Its Q1 2026 operating margin of 72% even exceeded TSMC’s (58.1%) and NVIDIA’s (65%).
Micron carries extremely high growth expectations: Bank of America raised its target price to $950 in May 2026. Samsung, meanwhile, holds the greatest potential for market share recovery as HBM4 mass production ramps up.
L2 Motherboard DRAM
This layer corresponds to conventional memory modules (“RAM sticks”).
Motherboard DRAM includes standard products such as DDR5, LPDDR, GDDR, and MR-DIMM. It currently accounts for the largest share of AI storage revenue, with the global DRAM market reaching ~$12.183 billion in 2025.
Samsung, SK Hynix, and Micron continue to dominate. As of Q4 2025, Samsung leads with 36.6% market share, SK Hynix follows at 32.9%, and Micron holds 22.9%.
With production capacity shifting toward higher-margin HBM, motherboard DRAM pricing power and profitability remain elevated. While per-unit margins are lower than HBM’s, its sheer scale makes it the largest absolute profit contributor.
L3 CXL Pooling Layer
CXL (Compute Express Link) enables DRAM to be “pooled” across an entire rack—not just confined to individual server motherboards.
Starting with CXL 3.x, all memory within a rack can be shared and dynamically allocated among multiple GPUs—addressing bottlenecks in AI inference, such as insufficient KV cache, vector database storage, and RAG indexing capacity.
The CXL memory module market was only $1.6 billion in 2024, but is projected to reach $23.7 billion by 2033. The oligopoly structure—dominated by Samsung, SK Hynix, and Micron—remains intact.
Within this layer, Astera Labs develops CXL-to-PCIe retimers and intelligent memory controllers, commanding ~55% share of this submarket. Its most recent quarter generated $308 million in revenue (+93% YoY), with a non-GAAP gross margin of 76.4% and net income up +85% YoY—truly extraordinary profitability.
L4 Enterprise SSDs: The biggest beneficiaries of the inference era
Enterprise NVMe SSDs serve as the primary storage layer for AI training checkpoints, RAG indexes, KV cache offloading, and model weight caching. High-capacity QLC SSDs have fully displaced HDDs from AI data lakes.
The enterprise SSD market reached ~$2.61 billion in 2025, growing at a 24% CAGR, and is projected to hit $7.6 billion by 2030.
Market share (by Q4 2025 revenue) stands at: Samsung 36.9%, SK Hynix (including Solidigm) 32.9%, Micron 14.0%, Kioxia 11.7%, SanDisk 4.4%—top five合计 ~90%.
The biggest shift here is the explosive adoption of QLC SSDs in AI inference workloads. Solidigm (a SK Hynix subsidiary) and Kioxia have already launched single-die 122 TB QLC SSDs; KV cache and RAG indexes are now spilling over from HBM into SSDs.
From a profit-pool perspective, enterprise SSDs lack HBM’s extreme gross margins—but they benefit from dual tailwinds: capacity-driven growth and inference expansion.
SK Hynix and Kioxia represent relatively pure-play beneficiaries. Samsung and SK Hynix, however, capture triple-layer upside—HBM + DRAM + NAND—making them comprehensive AI storage platform companies.
L5 NAS & Cloud Object Storage: The compounding pool of data gravity
NAS and cloud object storage form the outermost layer—hosting AI data lakes, training corpora, backups/archives, and cross-team collaboration. In 2025, the NAS market is ~$3.96 billion (17% CAGR), while cloud object storage is ~$0.91 billion (16% CAGR).
Major enterprise file-storage vendors include NetApp, Dell, HPE, and Huawei; SME-focused players include Synology and QNAP. Cloud object storage shares—estimated from IaaS provider market share—are AWS ~31–32%, Azure ~23–24%, Google Cloud ~11–12%, totaling ~65–70%.
Profit here stems primarily from long-term data hosting, egress fees, and ecosystem lock-in.
To summarize:
1) DRAM commands the largest TAM but lowest gross margin (30–40%); HBM’s TAM is only one-third of DRAM’s, yet its gross margin is double (>60%); CXL retimers command the smallest TAM but highest gross margin (>76%). The closer to compute, the scarcer—and more profitable—the layer.
2) Profit-pool growth is driven primarily by three areas: HBM (28% CAGR), enterprise SSDs (24% CAGR), and CXL pooling (37% CAGR).
3) Each layer features distinct business moats: HBM relies on technical barriers (TSV, CoWoS, yield ramp); CXL-related components rely on IP and certification (e.g., single-source retimer supply chains); services rely on switching costs.
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