Memory stocks fell 10%, but 2027 supply is already sold out.
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Memory stocks fell 10%, but 2027 supply is already sold out.
The fundamentals remain bright.
Navigating Web3 tides with focused insightsAuthor: Balder
Compiled by: TechFlow
TechFlow Editor's Note: Prices doubled in the first quarter, capacity sold out through 2027, and new contract prices are asking for multiples. The author believes the HBM-related memory shortage is not cyclical tightness, but a long-term supply-demand disconnect, a trend that cannot be bridged until 2029.
A Commodity No Longer Like a Commodity
For four decades, memory has been a textbook cyclical product: demand surges, factories built, prices plummet, cycle repeats. This rhythm is now clearly broken. In the first quarter of 2026, traditional DDR5—the boring, commoditized half of the DRAM market—contract prices skyrocketed 90% to 95% in a single quarter, not because PC buyers were ordering frantically, but because high bandwidth memory is swallowing the wafers DDR5 previously occupied. Three HBM suppliers—SK Hynix, Samsung, and Micron—have sold out all capacity for 2026, and 2027 quotas are being locked in. Samsung's memory division head warned in April that "severe shortages" would last at least until 2027, with customer fulfillment rates at historic lows; SK Group's chairman hinted pressure could extend to 2030.
And in the second quarter of 2026, negotiations for 2027 HBM4 supply contracts began—suppliers are seeking price increases of multiples, not percentages.
Stop and think about what this means. Price is a rationing mechanism. When a market must ration output for the next two years by doubling prices, this is not "tightness." This is the formal definition of demand exceeding supply—persistent, structural, and this article will argue, still underestimated. The following assertion is specific and falsifiable: under any defensible arithmetic, HBM bit supply cannot intersect with HBM bit demand before 2029. Forecasts will continue to be revised in one direction, because they are using tools for linear capacity increases to chase three exponential curves compounding with two-to-four-year delivery periods.
Every credible forecaster now admits the shortage. The argument of this article is that they are still underestimating its depth and duration—the reason is structural, not cyclical.
The Memory Wall: Twenty Years of Divergence Finally Come Due
The root cause is older than ChatGPT. For about twenty years, processor peak compute throughput has grown about 60,000 times—roughly doubling every eight months—while DRAM bandwidth has grown only about 100 times. Interconnect bandwidth performed worse. Hardware designers call this the memory wall: the pipeline feeding data to compute units has lagged behind the compute units themselves by three orders of magnitude.
Figure 1 — Compute throughput growth speed is approximately twice that of memory growth speed; over the past twenty years, the gap between the two has expanded 1,001,600 times. Transformer models (attention mechanism plus autoregressive decoding) are by far the most bandwidth-intensive major workloads deployed at scale, coinciding exactly with the bandwidth consumption limit side of this chart. (Source: Gholami et al., "Artificial Intelligence and the Memory Wall," IEEE Micro, 2024.)
Then the industry standardized the architecture least suited to this gap. Transformer inference is dominated by autoregressive decoding: to output each token, hardware must stream model weights and the entire accumulated KV cache from memory. Compute per byte moved is negligible. KAIST Professor Kim Jung-ho—often called the father of HBM—estimates that under AI workloads, GPUs are computing only 10% to 30% of the time; the rest is waiting for memory. Compute is abundant. Bytes per second are the scarce resource. This means every incremental AI capital expenditure dollar is essentially a purchase order for bandwidth—and today, bandwidth means HBM.
Demand: Three Exponential Curves, One Bottleneck
HBM bit demand is the product of two factors—accelerator unit shipments, and HBM gigabytes per accelerator—both are compounding. Start with content per package, because it is the cleanest public number:
Figure 2 — HBM capacity of NVIDIA flagship packages, 2020–2027 forecast. Rubin Ultra uses a four-chip package, equipped with 1 TB HBM4e memory (TrendForce's model shows memory capacity per GPU chip is 384 GB). In any case, memory capacity per socket is growing at 45%–55% annually—this must also be multiplied by double-digit to high double-digit shipment growth rates, and a second demand pool (Google TPU, AWS Trainium, and other ASICs) that barely existed two years ago. (Data Source: NVIDIA product roadmap disclosure; TrendForce, June 2026.)
Why is content per socket growing so violently? Because three independent demand curves are all releasing onto the same component.
Training: Memory Sets the Ceiling, Compute is Just Along for the Ride
Training frontier models is an exercise in trading memory for compute. The only reason technologies like ZeRO-3 exist: sharding parameters, gradients, and optimizer states across tens of thousands of GPUs, making the cluster's aggregated memory—not aggregated FLOPS—set the maximum trainable model size. The largest model you can build is a function of total VRAM. This makes HBM capacity, not compute, the constraint on the frontier itself.
Inference: Agents Turn KV Cache into the Protagonist
In the agent era, context is the means of production. Multi-turn conversations, tool calls, and long-term tasks routinely push working context to hundreds of thousands of tokens, and the KV cache—Transformer's working memory—grows linearly with each token for each concurrent user. The math is relentless:
Figure 3 — KV cache vs. context length for 70B-class models (80 layers, 8 KV heads, head dimension 128, FP16): 0.32 MB per token per sequence. In a practical service batch of 32 concurrent 128k token contexts, the KV cache alone occupies 1.28 TB—nine times the model weights—and the entire cache must be reread for every generated token. This is why HBM capacity per package, not FLOPS, determines how many users a GPU can serve. (Author calculation.)
Inference: Paradigm Shift Lands at the Worst Possible Stage
The third curve is the newest and steepest. As pre-training returns diminish, the frontier has shifted to test-time compute: inference models buy capability by generating tens to hundreds of times more chain-of-thought tokens for each task. Each of these tokens is produced during the decoding phase—at this stage, the GPU is not computing but streaming weights and KV cache from memory. Prefill consumes FLOPS; decoding consumes bandwidth; inference shifts the entire token mix towards decoding. The industry's path to higher intelligence routes all its new demand to the single most constrained resource in the data center.
Data confirms this. Google disclosed that its products processed about 480 trillion tokens in May 2025—reaching 1.3 quadrillion per month by October, nearly triple in five months. Token generation is the fastest-growing industrial output on Earth, and tokens are cast from memory bandwidth.
Conversion Tax: Why Capacity Cannot Simply "Catch Up"
The intuitive counterargument is that memory manufacturers have seen shortages before: spend enough capex, bits will appear. But HBM breaks this intuition in two places—wafers and calendar.
Wafers. HBM is not ordinary DRAM sold at a premium; it is a physically wasteful way of using wafers, tolerated because bandwidth is priceless. Die per bit is larger, thousands of TSVs occupy area, stacking eight to sixteen dies multiplies yield loss—one bad die can jeopardize the entire stack. Net result: producing one gigabyte of HBM consumes about four times the wafer capacity of one gigabyte of standard DRAM. TrendForce's forecast makes this tax visible:
Figure 4 — HBM share of DRAM wafer input vs. its share of DRAM bit output. For every 1 percentage point increase in HBM bit share, wafer share decreases by 2.3 percentage points. Fab transition to HBM slowly increases HBM bits while rapidly reducing traditional DRAM bits—the 90-95% skyrocket in DDR5 prices is precisely the manifestation of this trend. (Source: TrendForce, June 2026.)
Calendar. If wafer tax is a physical problem, lead time is a logistics problem. Total DRAM industry bit output grows only about 20% annually (Micron's own guidance for 2025 and 2026), because 2026 DRAM capex—up 14% to $61.3 billion—flows to node transitions, TSV equipment, hybrid bonding, and HBM conversion, not net new wafer starts. TrendForce is blunt: cleanroom space is the constraint, increased capex has "negligible impact" on 2026 bit supply growth. Truly new wafers arrive on factory schedules, and factory schedules are measured in years:
Data Source: Micron Fiscal 2026 Q1 Earnings Call; TrendForce; Company Announcements. Note that nothing on this list will have a substantial impact on total bit supply before 2027, while the largest increases will occur between 2028 and 2030.
So the supply side faces a closed loop: it can only cast HBM bits by burning wafers at a 4:1 exchange rate, it cannot quickly increase wafers, and every wafer it converts detonates prices elsewhere in the DRAM complex. This is not a supply curve catching up to demand. This is a supply curve being rationed in two shortages simultaneously.
Doing the Arithmetic: The Deficit Cannot Be Bridged
Put both sides together, using the suppliers' own numbers. Supply side: TrendForce's bit share path (8%→9%→13% of DRAM bits, 2025-2027) overlaid with about 20% total DRAM bit growth, means HBM bit supply grows about +35% in 2026 and about +73% in 2027—a truly heroic acceleration. Demand side: TrendForce predicts 2026 HBM demand growth of about 70%, driven by ASIC content jumps (96-192 GB→216-288 GB per chip), then Rubin Ultra's 384 GB-class GPUs and expanded TPU deployments accelerate again in 2027. Even giving supply the most optimistic path, and keeping demand at a conservative about 70-75% compound growth:
Figure 5 — HBM Bit Supply vs. Unconstrained Bit Demand (2025 = 100). Supply path based on TrendForce bit share estimates, based on Micron's forecast of 20% annual growth in total DRAM bits; Demand is 70% (TrendForce, 2026), thereafter 75% CAGR. The wedge area is the key point: even if supply accelerates growth to 73% annually, it can never intersect with the demand curve based on a higher base and faster compound growth—and this gap will widen further in 2028, which happens to be when new fabs finally come online. (Author model; assumptions stated; this gap persists for any demand CAGR ≥ 60%.)
Skeptical of anyone's model, including this one? Then use the market's own correction record. Forecast revisions are the cleanest evidence of systematic underestimation—and they only move in one direction:
Figure 6 — Micron Technology HBM Market (TAM) Forecast: December 2024 Outlook vs. December 2025 Outlook. In just twelve months, this supplier moved its $100 billion milestone target from 2030 to 2028, and nearly doubled the implied growth rate—raising cumulative HBM revenue from 2025 to 2030 from $378 billion to $555 billion (up 47%). TAM is a forecast of producible and sellable products; due to fulfillment rates being at historic lows, actual demand is higher than every line on the chart. (Data Source: Micron Technology disclosures; "The Next Platform," December 19, 2025.)
Pricing trends tell the same story from a third angle. HBM's annual negotiation contracts lagged so severely behind the 2025-26 spot explosion that by Q1 2026, the yield from one commodity DDR5 RDIMM wafer briefly exceeded one HBM wafer—this is precisely why suppliers are asking for multiples growth entering 2027 HBM4 negotiations. When scarce inputs can credibly threaten reallocation to their alternative shortage, you are not in a cycle. You are in an auction.
Three Honest Objections—And What They Actually Change
Objection One: Efficiency will shrink demand. This is a serious one. Because bandwidth is the bottleneck, the entire research community is attacking it: multi-query attention compresses KV cache by about 90%; sparse attention schemes stop rereading the entire context; KV quantization halves bytes again; speculative decoding restores arithmetic intensity; NVIDIA's Rubin CPX pushes prefill to cheaper GDDR7, precisely to save HBM for decoding. These are all real, any one of them could absorb a year of "exponential demand." But the record so far is pure Jevons paradox: every 10x drop in cost per token has expanded token consumption by more than 10x—Google's five-month triple happened during the fastest efficiency improvements in industry history. Efficiency changes the noise of the slope, not its sign. It is timing risk for any given quarter, not a refutation of the deficit.
Objection Two: Memory always looks structural at the top. Also fair. The upcycles of 1995, 2018, and 2021 each cast a "this time is different" argument about eighteen months before margins collapsed, because high prices historically triggered a wafer capacity arms race. But look where the money is going this time: capex is growing disciplinely by 14%, targeted at node migrations and HBM conversion within existing cleanrooms—according to Figure 4, this reduces traditional bits while increasing HBM bits. The classic depression mechanism is oversupply from new wafers; the earliest batch of truly new wafers arrives mid-2027, the big ones in 2028-2030. Oversupply scenarios are not impossible—they have a schedule. Its earliest credible window is 2029, and only if demand growth halves simultaneously.
Objection Three: China. CXMT holds high single-digit share in DRAM, concentrated in legacy nodes, and faces equipment restrictions on EUV-adjacent, TSV-intensive processes required for HBM4. Chinese supply is a real force in the next downturn for commodity DRAM; it is not a force in leading HBM for 2026-2028.
Note what none of these objections contest: direction. Bears argue when the gap closes. No one credible argues it doesn't exist anymore.
The Mean Itself Is Moving
Cyclical commodities are goods whose demand oscillates around a stable mean. HBM demand is the product of three simultaneously compounding curves—model size, context length, and inference volume—pressed against a supply system paying a 4:1 wafer tax and adding capacity with multi-year lead times. The mean is not stable; it is shifting exponentially, and suppliers' own correction history (Figure 6) shows that even those building factories cannot raise their estimates fast enough to keep up with it.
The assertion of this article is intentionally bounded: not saying memory will never cycle again, but that at least until 2028, HBM supply cannot intersect with demand—therefore prices, quotas, and multi-year prepayments will continue to assume rationing functions. The evidence is already on the books: fulfillment rates at historic lows, capacity sold out two years out, 2027 contract pricing already at multiples premium.
This assertion is also falsifiable. Three signals would break this judgment, readers should watch for them: 2027 HBM4 contract prices flat rather than multiples premium; supplier fulfillment rates returning to normal while inventory rebuilds; or capital expenditure clearly shifting from process and conversion spending to net new wafer starts earlier than planned. Before any of these signals appear, the baseline case still holds.
Betting on a return to cyclical normalcy is betting that three exponential curves will pause long enough for the 4:1 wafer tax and two-year fab construction cycle to catch up to them. Arithmetic tells us otherwise.
Betting on a return to cyclical normalcy is betting that three exponential curves will pause long enough for the 4:1 wafer tax and two-year fab construction cycle to catch up to them. Arithmetic tells us otherwise.
Sources and Notes: TrendForce (June 2, 2026; November 13, 2025; December 26, 2025 via Commercial Times); Micron Fiscal 2026 Q1 Earnings Call and TAM disclosures (via The Next Platform, December 19, 2025); Tom's Hardware reports on Samsung/SK Hynix shortage warnings (May 2026); Gholami et al., "AI and the Memory Wall," IEEE Micro (2024); Kim Jung-ho (KAIST) public lectures; Google/Alphabet token volume disclosures (2025); DeepSeek-V2/V3 technical reports; NVIDIA Rubin CPX launch (September 2025); SemiAnalysis, "Memory Mania" (February 2026). Figures 3 and 5 are author calculations, assumptions stated in figure notes.
Disclosure: This article is independent analysis and opinion, for reference only. This article does not constitute investment advice, predictions herein have significant uncertainty. Readers should verify data against original sources before making decisions.
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